(a) Field of the Invention
The present invention relates to a semiconductor device having a fuse and, more particularly, to an improvement of the structure of the fuse element in a fuse.
(b) Description of the Related Art
Most of semiconductor devices such as a DRAM or SRAM have fuse blocks for use in redundancy circuits. When a defect is found in a memory cell during a product test, the defective memory cell is replaced with a redundancy memory cell by cutting an associated fuse element while irradiating the fuse element with a laser beam.
The fuse block is also used in a multi-mode semiconductor memory device such as DRAM, wherein a plurality of control circuits are provided each for effecting one of a plurality of operational modes such as a static column mode or a high-speed phase mode. One of the control circuits is selected for effecting a specified operational mode, after fabrication of the semiconductor device, by cutting the fuse elements other than the specified fuse element, whereby the other control circuits are inactivated.
Along with the increase of demand for higher integration and finer patterning of semiconductor devices, a multi-level interconnect structure is increasingly used wherein a plurality of interconnect layers are alternately stacked with a plurality of interlevel dielectric layers, and connected together by using via plugs embedded in the dielectric layers. The multi-level interconnect structure includes a fuse block including a plurality of fuses each having a pair of terminals and a fuse element, which are formed on an underlying dielectric film and covered by an overlying dielectric protective film. The underlying dielectric film is generally formed as a top interlevel dielectric layer on which the top interconnect layer is formed.
FIG. 1 shows a conventional structure of the fuse block such as described in Patent Publication JP-A-11-17011. The fuse block, generally designated by numeral 10, has a plurality of fuses each including a pair of fuse terminals 18A and 18B and a fuse element 12, which are formed on an underlying dielectric film 14 as a common layer with interconnect lines such as signal lines 16A, 16B and 16C. Depiction of the overlying protective film is omitted therein for simplification purpose. The fuse element 12 has a smaller thickness and bridges the fuse terminals 18A and 18B having a larger thickness, which is comparable to the thickness of the interconnect lines.
Each of the fuse terminals 18A and 18B and the interconnect lines 16A, 16B and 16C has a two-layer structure including an aluminum (Al) body film 20 and a TiN protective film, whereas the fuse element 12 is implemented by a single layer of the TiN film. The TiN film 12 has a lower reflectance and thus a higher absorbance compared to the Al film, and is readily fused by a laser beam having a relatively lower energy level.
The fuse structure is fabricated as detailed below. Referring to FIG. 2A, an Al film 22 is formed on an underlying interlevel dielectric film 16 overlying a semiconductor substrate 100. The Al film 22 is patterned to form interconnect lines 20 including fuse terminals 18A and 18B, as shown in FIG. 2B, followed by depositing a TiN film 24 on the entire surface including the surfaces of the interconnect lines, as shown in FIG. 2C. The TiN film is then patterned to form a two-layer structure of the interconnect liens 20 as well as the fuse elements 12 each connecting the pair of fuse terminals 18A and 18B together.
With the trend for reduction of the chip size of the semiconductor device, the occupied area for the interconnect lines and the fuse structure as well as the line space between the fuses and between the fuse terminals should be reduced. The reduction of the occupied area for the fuse structure has some problems.
First, the reduction of the line space reduces the allowable positioning margin of the etching mask used for patterning the TiN film, thereby generating defects in the fuse terminals and the interconnect lines.
FIGS. 3A and 3B show examples of the defects caused by the reduction of the positioning margin. In FIG. 3A, a misalignment occurs between the etching mask 26 and Al films 20 of the interconnect lines, and accordingly the Al film 20 is slightly etched after the patterning to cause reduction of the effective sectional area for the interconnect lines, as shown in FIG. 3B, thereby increasing the electric resistance of the interconnect lines.
Second, the reduction of the line space raises the aspect ratio during the patterning step for the TiN film, wherein the aspect ratio is defined as the ratio of the line thickness to the line space. The higher aspect ratio is likely to cause, as shown in FIG. 4, an incomplete etching of the refractive metal film 24 at the gap between the Al films 20A and 20B of the interconnect lines, thereby generating a short circuit failure therebetween.